1. Field of Invention
This invention refers to flash memory and in particular to the automatic programing of flash memory cells.
2. Description of Related Art
In an electrically erasable programmable read only memories (EEPROM), there exists a floating gate in each memory cell which is charged by hot elections injected onto the floating gate to store data into the memory cell. These floating gales are erased by a Fowler-Nordheim tunneling technique where a second gate called a control gate is grounded or negative biased and the drain is set at a high voltage. The injection of charge on a floating gate takes a period of time to accumulate the necessary amount of charge to establish the proper threshold voltage. A mechanism is therefore needed to determine when programming of floating gate device has been accomplished.
In U.S. Pat. No. 5,712,815 (Bill et al.) and U.S. Pat. No. 5,724,284 (Bill et al.) a method of programming a flash EEPROM uses reference cells to monitor and disable programming. Multiple threshold voltages are used in the memory cell to allow one erased state and three programmable states. The multiple threshold states are established using a reference cell array. Two transistors are placed in the bit line path to act as a switch and a current source. Bit line voltage is monitored by a reference voltage. The conventional memory cell requires high voltages and high programming currents resulting in a low bit line voltage and making it difficult to obtain adequate sensing margins for multilevel data.
Referring to U.S. Pat. No. 5,684,741 (Talreja), a current mirror is used to monitor current through an EEPROM memory cell that provides a signal to a differential amplifier. The device current during program is compared to a programmed cell current to determined when to stop programming of the memory cell. In U.S. Pat. No. 5,532,964 (Cernea et al.) a method and circuit using a novel sense amplifier is used to determine when programming of an EEPROM cell has been accomplished. The sense amplifier and associated programming circuitry are shared with a plurality of bit lines through a bit line selection circuit. In both U.S. Pat. No. 5,684,741 and U.S. Pat. No. 5,532,964 the sensing circuits are not compact enough to allow future implementation of wide page mode programming of every bit line in an array.
The programming of EEPROM cells is a relatively slow process because charge is injected onto a floating gate by means of the channel hot electron process. As charge is built up on the floating gate, the threshold voltage of the transistor with the floating gate rises and slows the process of inducing charge onto the floating gate. Without a method to detect when programming of an EEPROM cell has been accomplished, the process is even longer because a "program and then read method" must be used to determine if data has been programmed to the correct threshold voltage. There is also the potential of over programming the cell and reducing the number of times a particular cell can be reprogrammed because of charge buildup. A means by which the process of writing data to an EEPROM cell can be done quickly and efficiently is needed that automatically terminates programming when a cell is programmed, providing consistent programming with longevity of repeated erasure and programming.